From the 90 nm CMOS integrated circuit technique, Strain Channel Engineering for the purpose of increasing the channel carrier mobility plays an increasingly important role with continuous reduction in the device feature size. Various strain techniques and new materials have been integrated into the device process, namely, a compressive stress or a tensile stress is introduced in the channel direction so as to increase the carrier mobility and improve device performance.
For example, for 90 nm process node, compressive stress in a PMOS device is provided by using embedded SiGe (e-SiGe) source/drain or using a (100) crystal orientation substrate in combination with a tensile stress contact etch stop layer (tCESL); for 65 nm process node, the first generation source/drain stress memorization technique (SMT×1) is further adopted on the basis of the 90 nm process node, for example, a dual contact etch stop layer is used; for 45 nm process node, the second generation source/drain stress memorization technique (SMT×2) is used on the basis of the previous technique, for example, e-SiGe technique may be used in combination with a tCESL or a dual CESL, besides, Stress Proximity Technique (SPT) may be used, moreover, a (110)-plane substrate is adopted for PMOS and a (100)-plane substrate is adopted for NMOS; after 32 nm process node, the third generation source/drain stress memorization technique (SMT×3) is used, for example, embedded SiC source/drain is used on the basis of the previous techniques to enhance the tensile stress in a NMOS device.
In addition, in order to increase the carrier mobility of the channel region, various non-silicon based materials can be used, for example, Ge, GaAs, InP, GaSb, InAs, InSb whose (electron) mobility progressively increase.
Moreover, technology of introducing stress to a channel can be realized by controlling a material or a cross-section shape of the channel or the spacer apart from changing the materials of the substrate or the source/drain. One example is that a dual stress liner (DSL) technique can be adopted. Another example is that a tensile stressed SiNx layer spacer can be adopted for a NMOS and a compressive stressed spacer can be adopted for a PMOS. Still another example is that the cross-section of the embedded SiGe source/drain is manufactured as a Σ-shape so as to improve the channel stress of the PMOS.
Generally speaking, the above-mentioned various channel strain techniques that have already been widely used can basically be divided into two categories, i.e. (biaxial) global substrate strain and uniaxial process induced channel strain. The biaxial global strain technique requires to change the substrate material, so it involves problems concerning material growth defects (e.g. energy level change, state density change, carrier concentration change, etc. caused by the change in substrate material), problems concerning compatibility with the CMOS device technique, problems concerning the interface state of the interface between the substrate and the ultra-thin high-K oxide layer, and the like. In contrast, the uniaxial local strain technique uses a process-induced strain and does not require to change the substrate, so the channel strain can be selected effectively without incurring problems concerning such as material growth defects and CMOS process compatibility, and there is a good interface between the substrate and the ultra-thin high-K oxide layer. As a result, the uniaxial local strain technique gradually becomes the mainstream technique.
In spite of the above-mentioned defects, the biaxial global strain technique can increase the carrier mobility to a great extent effectively due to its ability to provide good strain in two axial directions. If the biaxial process can be improved to overcome the above-mentioned defects and realize good fully strained channel, and to overcome the defects in the existing techniques while making full use of the advantages of the biaxial process, it will help to further improve the device performance and reduce the cost.